Preface xiv TOPIC I: OVERVIEW OF VLSI DESIGN METHODOLOGY 1 I.1 Methodology Guidelines for Logical and Physical Design Hierarchy Correspondence 6 I.2 Managing Inter-Block Glue Logic 8 Chapter 1 Introduction 13 1.1 Definitions 13 1.2 Intellectual Property (IP) Models 21 1.3 Tapeout and NRE Fabrication Cost 42 1.4 Fabrication Technology 44 1.5 Power and Clock Domains On-chip 105 1.

6 Physical Design Planning 113 1.7 Summary 126 References 127 Further Research 129 Chapter 2 VLSI Design Methodology 131 2.1 IP Design Methodology 131 2.2 SoC Physical Design Methodology 141 2.3 EDA Tool and Release Flow Management 165 2.4 Design Methodology "Trailblazing" and Reference Flows 168 2.5 Design Data Management (DDM) 171 2.6 Power and Clock Domain Management 175 2.

7 Design for Testability (DFT) 177 2.8 Design-for-Manufacturability (DFM) and Design-for-Yield (DFY) Requirements 184 2.9 Design Optimization 185 2.10 Methodology Checks 186 References 190 Further Research 190 Chapter 3 Hierarchical Design Decomposition 193 3.1 Logical-to-Physical Correspondence 193 3.2 Division of SRAM Array Versus Non-Array Functionality 197 3.3 Division of Dataflow and Control Flow Functionality 198 3.4 Design Block Size for Logic Synthesis and Physical Design 202 3.

5 Power and Clock Domain Considerations 206 3.6 Opportunities for Reuse of Hierarchical Units 207 3.7 Automated Test Pattern Generation (ATPG) Limitations 208 3.8 Intangibles 211 3.9 The Impact of Changes to the SoC Model Hierarchy During Design 212 3.10 Generating Hierarchical Electrical Abstracts Versus Top-Level Flat Analysis 214 3.11 Methodologies for Top-Level Logical and Physical Hierarchies 216 3.12 Summary 218 References 219 Further Research 219 TOPIC II: MODELING 221 Chapter 4 Cell and IP Modeling 223 4.

1 Functional Modeling for Cells and IP 223 4.2 Physical Models for Library Cells 240 4.3 Library Cell Models for Analysis Flows 241 4.4 Design for End-of-Life (EOL) Circuit Parameter Drift 251 4.5 Summary 253 References 253 Further Research 254 TOPIC III: DESIGN VALIDATION 257 Chapter 5 Characteristics of Functional Validation 259 5.1 Software Simulation 259 5.2 Testbench Stimulus Development 262 5.3 Hardware-Accelerated Simulation: Emulation and Prototyping 268 5.

4 Behavioral Co-simulation 275 5.5 Switch-Level and Symbolic Simulation 275 5.6 Simulation Throughput and Resource Planning 281 5.7 Validation of Production Test Patterns 284 5.8 Event Trace Logging 288 5.9 Model Coverage Analysis 289 5.10 Switching Activity Factor Estimates for Power Dissipation Analysis 295 5.11 Summary 296 References 297 Further Research 298 Chapter 6 Characteristics of Formal Equivalency Verification 301 6.

1 RTL Combinational Model Equivalency 301 6.2 State Mapping for Equivalency 302 6.3 Combinational Logic Cone Analysis 305 6.4 Use of Model Input Assertions for Equivalency 306 6.5 Sequential Model Equivalency 307 6.6 Functional and Test-Mode Equivalence Verification 309 6.7 Array Equivalence Verification 310 6.8 Summary 313 References 314 Further Research 314 TOPIC IV: DESIGN IMPLEMENTATION 317 Chapter 7 Logic Synthesis 319 7.

1 Level of Hardware Description Language Modeling 319 7.2 Generation and Verification of Timing Constraints 320 7.3 Technology Mapping to the Cell Library 328 7.4 Signal Repowering and "High-Fan-out" Net Synthesis (HFNS) 335 7.5 Post-Synthesis Netlist Characteristics 339 7.6 Synthesis with a Power Format File 340 7.7 Post-Technology Mapping Optimizations for Timing and Power 343 7.8 Hold Timing Optimization 348 7.

9 Clock Tree Synthesis (CTS) 350 7.10 Integration of Hard IP Macros in Synthesis 353 7.11 Low-Effort Synthesis (LES) Methodology 354 7.12 Summary 359 References 360 Further Research 360 Chapter 8 Placement 363 8.1 Global Floorplanning of Hierarchical Units 363 8.2 Parasitic Interconnect Estimation 366 8.3 Cell Placement 367 8.4 Clock Tree Local Buffer Placement 369 8.

5 Summary 370 References 370 Further Research 370 Chapter 9 Routing 373 9.1 Routing Introduction 373 9.2 Global and Detailed Routing Phases 378 9.3 Back End Of Line Interconnect "Stacks" 383 9.4 Routing Optimizations 387 9.5 Summary 399 References 400 Further Research 400 TOPIC V: ELECTRICAL ANALYSIS 403 Chapter 10 Layout Parasitic Extraction and Electrical Modeling 405 10.1 Introduction 405 10.2 Cell- and Transistor-Level Parasitic Modeling for Cell Characterization 411 10.

3 Decoupling Capacitance Calculation for Power Grid Analysis 431 10.4 Interconnect Extraction 433 10.5 "Selected Net" Extraction Options 438 10.6 RLC Modeling 439 10.7 Summary 439 References 440 Further Research 442 Chapter 11 Timing Analysis 443 11.1 Cell Delay Calculation 443 11.2 Interconnect Delay Calculation 446 11.3 Electrical Design Checks 452 11.

4 Static Timing Analysis 453 11.5 Summary 469 References 470 Further Research 472 Chapter 12 Noise Analysis 475 12.1 Introduction to Noise Analysis 475 12.2 Static Noise Analysis, Part I 476 12.3 Noise Impact on Delay 481 12.4 Electrical Models for Static Noise Analysis 485 12.5 Static Noise Analysis, Part II 488 12.6 Summary 491 References 492 Further Research 493 Chapter 13 Power Analysis 495 13.

1 Introduction to Power Analysis 495 13.2 Models for Switching Activity Power Dissipation 497 13.3 IP Power Models 501 13.4 Device Self-Heat Models 502 13.5 Design-for-Power Feedback from Power Analysis 504 13.6 Summary 505 References 506 Further Research 506 Chapter 14 Power Rail Vo.