1. Introduction to FPGA design a. Xilinx FPGA architecture and design flow b. Altera FPGA architecture and design flow c. SOC design and flow and use of HDL 2. Introduction to HDL a. VHDL Language and applications b. Verilog Evolution and practical applications c.

SystemVerilog and use for design d. SystemVerilog and use for verification 3. Introduction to SystemVerilog i. Data Types ii. Programming model iii. Parameterized model iv. Examples 4. Programming using SystemVerilog a.

Operators b. Loops c. Task and functions d. Procedural blocks e. Decision control statements f. Casting using SystemVerilog 5. Combinational design using SystemVerilog a. Adders b.

Subtractors c. Multipliers d. Dividers e. MUX f. Demux g. Decoder h. Encoder 6. Sequential design using SystemVerilog a.

Latches b. Flip-flops c. Counters i. BCD ii. Binary iii. Gray iv. Johnson v. Ring d.

Shift Registers i. SISO ii. PIPO iii. SIPO iv. PISO 7. RTL design using SystemVerilog a. Synthesizable systemverilog constructs b. Interfaces c.

Netlist d. Synthesis using SystemVerilog e. Complex Designs using SystemVerilog i. ALU design ii. Parity generators iii. Processor core logic design f. FSM Using SystemVerilog i. Moore machines ii.

Mealy machines 8. Verification using SystemVerilog a. Verification architecture b. Verification planning c. Verification Constructs d. Coverage goals e. Case study 9. Design Implementation using FPGA a.

8-bit Processor design using SystemVerilog i. Implementation using FPGA ii. Design verification iii. System Testing Appendix.