Phase-Locked Loops : System Perspectives and Circuit Design Aspects

Click to enlarge

Author(s):	Rhee, Woogeun
ISBN No.:	9781119909040
Pages:	384
Year:	202401
Format:	Trade Cloth (Hard Cover)
Price:	$ 193.20
Dispatch delay:	Dispatched between 7 to 15 days
Status:	Available

Qty: Add to Cart

Synopsis
Table of contents
Full Details

ABOUT THE AUTHOR PREFACE xi 1 INTRODUCTION 1 1.1 PHASE-LOCK TECHNIQUE 1 1.2 KEY PROPERTIES AND APPLICATIONS 2 1.2.1 Frequency Synthesis 3 1.2.2 Clock-and-Data Recovery 3 1.2.

3 Synchronization 4 1.2.4 Modulation and Demodulation 4 1.2.5 Carrier Recovery 4 1.2.6 Frequency Translation 5 1.3 ORGANIZATION AND SCOPE OF THE BOOK 6 I PHASE-LOCK BASICS 2 LINEAR MODEL AND LOOP DYNAMICS 8 2.

1 LINEAR MODEL OF THE PLL 8 2.2 FEEDBACK SYSTEM 10 2.2.1 Basics of Feedback Loop 10 2.2.2 Stability 11 2.3 LOOP DYNAMICS OF THE PLL 13 2.3.

1 First-Order Type 1 PLL 13 2.3.2 Second-Order Type 1 PLL 14 2.3.3 Second-Order Type 2 PLL 15 2.3.4 Natural Frequency and Damping Ratio 17 2.3.

5 High-Order PLLs 19 2.3.6 Bandwidth of PLL 19 2.3.7 Loop Gain and Natural Frequency 20 2.3.8 3-dB Bandwidth 20 2.3.

9 Noise Bandwidth 21 2.4 NOISE TRANSFER FUNCTION 22 2.5 CHARGE-PUMP PLL 25 2.5.1 High-Order CP-PLL 27 2.5.2 Control of Loop Parameters 28 2.5.

3 Another Role of Shunt Capacitor 30 2.6 OTHER DESIGN CONSIDERATIONS 33 2.6.1 Time-Continuous Approximation 33 2.6.2 Practical Design Aspects 34 3 TRANSIENT RESPONSE 36 3.1 LINEAR TRANSIENT PERFORMANCE 37 3.1.

1 Steady-State Phase Response 37 3.1.2 Transient Phase Response 39 3.1.3 Settling Time 40 3.2 NONINEAR TRANSIENT PERFORMANCE 44 3.2.1 Hold-In Range 45 3.

2.2 Pull-In Range 46 3.2.3 Lock-In Range 47 3.2.4 Nonlinear Phase Acquisition 48 3.3 PRACTICAL DESIGN ASPECTS 48 3.3.

1 Type 1 and Type 2 PLLs with Frequency-Step Input 49 3.3.2 State-Variable Model 50 3.3.3 Two-Path Control in the CP-PLL 51 3.3.4 Two-Path Control in DPLL 53 3.3.

5 Slew Rate of CP-PLL 54 3.3.6 Effect of the PFD Turn-On Time 56 II SYSTEM PERSPECTIVES 4 FREQUENCY AND SPECTRAL PURITY 58 4.1 SPUR GENERATION AND MODULATION 58 4.1.1 Spurious Signal (Spur) 58 4.1.2 Reference Spur 66 4.

2 PHASE NOISE AND RANDOM JITTER 75 4.2.1 Phase Noise Generation and Measurement 75 4.2.2 Integrated Phase Noise 80 4.2.3 Optimum Loop Bandwidth for Phase Noise 83 5 APPLCIATION ASPECTS 88 5.1 FREQUENCY SYNTHESIS 89 5.

1.1 Direct Frequency Synthesis 89 5.1.2 Indirect Frequency Synthesis by Phase Lock 90 5.1.3 Frequency Synthesizer Architectures for Fine Resolution 92 5.1.4 System Design Aspects for Frequency Synthesis 94 5.

2 CLOCK-AND-DATA RECOVERY 98 5.2.1 Wireline Transceiver with Serial Link 98 5.2.2 Clock Recovery and Data Retiming by PLL 99 5.3 CLOCK GENERATION 105 5.3.1 System Design Aspects 105 5.

3.2 Clock Jitter for Wireline Systems 108 5.4 SYNCHRONIZATION 111 5.4.1 PLL for Clock De-Skewing 111 5.4.2 Delay-Locked Loop 113 III BUILDING CIRCUITS 6 PHASE DETECTORS 118 6.1 NON-MEMORY PHASE DETECTORS 118 6.

1.1 Multiplier PD 118 6.1.2 Exclusive-OR PD 119 6.1.3 Flip-Flop PD 120 6.1.4 Sample-and-Hold PD 121 6.

1.5 Sub-Sampling PD 122 6.2 PHASE-FREQUENCY DETECTOR 123 6.2.1 Operation Principle 123 6.2.2 Dead-Zone Problem 125 6.2.

3 Effect of the PFD Turn-On Time on PLL Settling 126 6.2.4 Noise Performance of PFD 127 6.3 CHARGE PUMP 128 6.3.1 Circuit Design Considerations 128 6.3.2 Single-Ended Charge Pump Circuits 132 6.

3.3 Semi- and Fully-Differential Charge Pump Circuits 135 6.3.4 Design of Differential Loop Filter 137 7 VOLTAGE-CONTROLLED OSCILLATORS 142 7.1 OSCILLATOR BASICS 143 7.1.1 Oscillation Condition 143 7.1.

2 Quality Factor 144 7.1.3 Frequency Stability 147 7.1.4 Effect of Circuit Noise 148 7.1.5 Leeson''s Model and Figure-of-Merit 149 7.1.

6 Effect of Noise Coupling 150 7.2 LC VCO 151 7.2.1 Design Considerations 151 7.2.2 LC VCO Circuit Topologies 159 7.3 RING VCO 165 7.3.

1 Design Aspects 165 7.3.2 Phase Noise 166 7.3.3 Circuit Implementation 170 7.4 RELAXATION VCO 174 7.4.1 Relaxation Oscillator with Ground Capacitor 174 7.

4.2 Relaxation Oscillator with Floating Capacitor 175 8 FREQUENCY DIVIDERS 180 8.1 BASIC OPERATION 180 8.1.1 Frequency Division with Prescaler 180 8.1.2 Standard Configuration of Prescaler-Based Frequency Divider 183 8.1.

3 Operation Principle of Dual-Modulus Divider 185 8.2 CIRCUIT DESIGN CONSIDERATIONS 189 8.2.1 Frequency Divider with Standard Logic Circuits 189 8.2.2 Frequency Divider with Current-Mode Logic Circuits 190 8.2.3 Critical Path of Modulus Control 195 8.

3 OTHER TOPOLOGIES 197 8.3.1 Phase-Selection Divider.

To be able to view the table of contents for this publication then please subscribe by clicking the button below...

To be able to view the full description for this publication then please subscribe by clicking the button below...