Foreword Preface Acknowledgments About the Author Acronyms and Glossary Introduction Objectives Introduction to SATA Serial Interface Advantage The Move to Serial Technology Serial ATA Goals and Objectives SATA Benefits Almost Exactly 10 Years Later Introduction to SATA Express Storage Evolution Serial ATA System Connection Model SATA Connectivity External SATA Storage SATA High Availability SATA Applications¿More than Disk Storage Client and Enterprise SATA Devices mSATA M.2 SATA microSSD¿ SATA Universal Storage Module Summary SATA Technical Overview Objectives What Is ATA? Physical Interface Specifications and Standards Industry Standards SATA Specifications SATA Layered Architecture The I/O Register Model Host and Device Register Parallel Register Operations PATA I/O Process Flow Register Formats Command Register Status Register Error Register Device Register CHS and LBA Addressing CHS Addressing LBA Addressing ATA Protocols Data Transfer Modes ¿ PIO Data Transfer Modes¿DMA Parallel ATA Emulation SATA Technical Overview Serial Links Differential Signaling Encoding 8b10b Encoding Encoding Characteristics SATA Primitives and Data Words SATA Primitives Idle Serial Links Frame Transmission Link Layer Protocol Link Layer Protocol Summary Transport Layer Protocol Application Layer CHS to LBA Translation General Feature Set Commands Summary Review Questions SATA Application Layer Objectives SATA Application/Command Layer Command Set Register Delivered Command Sector Addressing Command Codes from ATA/ATAPI Command Set R4I General Feature Set Commands Optional General Feature Set Commands PACKET General Feature Set Commands Unique PACKET Command Feature Set Power Management Feature Set PACKET Power Management Feature Set Security Mode Feature Set SMART Feature Set Commands Removable Media Status Notification Feature Set Removable Media Feature Set CompactFlash¿ Association (CFA) Feature Set 48-Bit Address Feature Set Streaming Feature Set General Purpose Logging Feature Set Overlapped Feature Set Command Descriptions Command Overview Device Configuration Review Questions SATA Transport Layer Objectives SATA Transport Layer Transport Layer Services Frame Information Structure (FIS) FIS Types Register ¿ Host to Device FIS Register ¿ Device to Host FIS Set Device Bits FIS First-Party DMA Setup FIS DMA Activate FIS SATA II Changes to DMA Transport Data FIS BIST Activate FIS PIO Setup FIS Changes to FISes for Port Multipliers Serial Interface Host Adapter Registers Overview SCR Mapping and Organization SStatus, SError, and SControl Registers Command Processing Examples Legacy DMA Read by Host from Device Legacy DMA Write by Host to Device PIO Data Read from the Device PIO Data Write to the Device WRITE DMA QUEUED Example ATAPI PACKET Commands with PIO Data-In ATAPI PACKET Commands with PIO Data-Out ATAPI PACKET Commands with DMA Data-In ATAPI PACKET Commands with DMA Data-Out First-Party DMA Read of Host Memory by Device First-Party DMA Write of Host Memory by Device PIO Data Read from the Device ¿ Odd Word Count PIO Data Write to the Device ¿ Odd Word Count First-Party DMA Read of Host Memory by Device ¿Odd Word Count First-Party DMA Write of Host Memory by Device ¿Odd Word Count Native Command Queuing Introduction to NCQ Benefits of Native Command Queuing (NCQ) Detailed Description of NCQ How Applications Take Advantage of Queuing Conclusion NCQ Example NCQ Queue Management ABORT NCQ QUEUE Subcommand (0h) NCQ Deadline Handling Subcommand (1h) Chapter Review SATA Link Layer Objectives Link Layer Responsibilities Frame Transmission Topics Frame Reception Topics Transmission Methodology SATA Structures DWORDs Primitive Structure Frame Structure Primitives Primitive Encoding Detailed Primitives Descriptions Scrambling Frame Content Scrambling Link Layer Traces Encoding Method Notation and Conventions Encoding Characteristics Running Disparity 8b10b Valid Encoded Characters CRC Calculation Review Questions Physical Layer Objectives PHY Layer Services Out of Band (OOB) Signaling 8 OOB Signaling Protocol Power-Up and COMRESET Timing Link Speeds Resets and Signatures OOB Signal Detection Logic Interface Power States BIST (Built-In Self-Test) Loopback Testing Loopback¿Far End Retimed Loopback¿Far-End Analog (Optional) Loopback¿Near-End Analog (Optional) Impedance Matching Physical Layer Electronics (PHY) Electrical Specifications Electrical Goals, Objectives, and Constraints Rise/Fall Times Review Questions Error Handling Objectives Error Handling Error Handling Responses Phy Error Handling Overview Link Error Handling Overview Transport Error Handling Software Error Handling Overview State Diagram Conventions Power-on and COMRESET Protocol Diagram Host Phy Initialization State Machine Review Cables and Connectors Objectives SATA Connectivity for Device Storage Client and Enterprise SATA Devices Micro SATA mSATA LIF-SATA microSSD¿ M.2 SATA SATA Universal Storage Module (USM) SATA Cabling Cable Assemblies Internal 1 m Cabled Host to Device SATA Cable External SATA SATA Express SATA Express Connector Goals SATA Express Is Pure PCIe SATA Express Scope Hot Plugging Review Port Multipliers and Selectors Objectives Port Multiplier Port Multiplier Characteristics PM Operational Overview Addressing Mechanism Policies FIS Delivery Mechanisms Starting a FIS Transmission Booting with Legacy Software Hot Plug Events Link Power Management Reducing Context Switching Complexity Error Handling and Recovery Command Timeout Disabled Device Port Invalid Device Port Address Invalid CRC for Device-Initiated Transfer Data Corruption Command-Based Switching Port Multiplier Registers General Status and Control Registers Status Information and Control Features Supported Port Status and Control Registers Port Multiplier Command Read Port Multiplier Write Port Multiplier Serial ATA Superset Registers Enhancements Resets and Software Initialization Sequences Examples of Software Initialization Sequences Port Multiplier Aware Software Port Multiplier Discovery and Device Enumeration Switching Type Examples Command-Based Switching FIS-Based Switching Port Selectors Port Selector Definitions, Abbreviations, and Conventions Port Selector Overview Active Port Selection Side-Band Port Selection Behavior During a Change of Active Port Behavior and Policies Control State Machine BIST Support Flow Control Signaling Latency Power Management Power-up and Resets Power-up Resets Host Implementation Software Method for Protocol-Based Selection (Informative) Summary Software and Drivers Objectives Storage I/O Stack I/O Manager File System Volume Manager Hardware SATA and SATA Express SATA Configurations Advanced Host Channel Interface System Memory Structure AHCI Encompasses a PCI Device HBA Configuration Registers HBA Memory Registers System Memory Model Received FIS Structure Command List Structure Summary SATA and SATA Express Architectures Review Advanced Host Channel Interface (AHCI) Review PCI Header and Configuration Space Review Memory Registers Review HBA Memory Space Usage Review Port Memory Usage Review Command List Structure Review Appendix A: Chapter Review Answers Index.